Reliability and Power Analysis of FinFET Based SRAM

Demand for accommodating more and new functionalities within a single chip such as SOC needs novel devices architecture FinFET instead of MOSFET. emerged non-planar, multigate device to overcome short channel effects subthreshold swing deterioration, drain induced barrier lowering threshold voltage roll-off which degrade circuit performance. As the need technology is mounting in electronic gadgets important parameters are taken into consideration low leakage, high reliability, power dissipation, operating speed. Reliability one key considerations converting proof concept reality. In this work reliability studied experimentally according ITRS (international roadmap semiconductors) using several standard test protocols multiple current stressing, harsher environment conditions, effect electromigration. Furthermore, analysis based SRAM done by 7 nm BSIM-CMG Predictive model files (PTM) mentor graphics tool. The showed less delay compared existing conventional MOSFET SRAM.